1. Field of the Invention
The present invention relates generally to methods for forming metal silicide layers within microelectronics fabrications. More particularly, the present invention relates to thermal annealing methods for forming metal silicide layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications are formed from microelectronics substrates over which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectrics layers.
As microelectronics fabrication integration levels have increased and microelectronics device and patterned microelectronics conductor layer dimensions have decreased, it has become increasingly more important to form within microelectronics fabrications patterned microelectronics conductor layers to which uniformly low resistance connections may be made. In order to form such uniformly low contact resistance connections to patterned microelectronics conductor layers within microelectronics fabrications, it is common in the art of microelectronics fabrication to employ a patterned metal silicide layer, often formed in a self aligned fashion, formed upon the patterned microelectronics conductor layer.
While the use of patterned metal silicide layers as low contact resistance layers formed upon patterned microelectronics conductor layers is thus common in the art of microelectronics fabrication, the use of patterned metal silicide layers as low contact resistance layers formed upon patterned microelectronics conductor layers is nonetheless not entirely without problems in the art of microelectronics fabrication. In particular, it is often difficult to form such patterned metal silicide layers simultaneously with uniformly low contact resistance and with minimal process complexity.
It is thus towards the goal of forming within microelectronics fabrications metal silicide layers with uniformly low contact resistance and minimal process complexity that the present invention is directed.
Various methods and microelectronics structures have been disclosed in the art of microelectronics fabrication for forming metal silicide layers and/or for using metal silicide layers within microelectronics fabrications.
For example, Lehrer, in U.S. Pat. No. 4,359,490, discloses a chemical vapor deposition (CVD) method for forming at a comparatively low deposition temperature a metal silicide layer within a microelectronics fabrication. The chemical vapor deposition (CVD) method is a chemical vapor deposition (CVD) co-deposition method which employs silane as a silicon source material, simultaneously with an appropriate metal chloride vapor as a metal source material, when forming the metal silicide layer.
In addition, West et al., in U.S. Pat. No. 4,814,294, discloses a chemical vapor deposition (CVD) method for forming cobalt silicide layers of various atomic compositions within microelectronics fabrications. The chemical vapor deposition (CVD) method simultaneously employs a cobalt carbonyl as a cobalt source material and a silane or a halogenated silane as a silicon source material when forming the cobalt silicide layers.
Further, Zeininger et al., in U.S. Pat. No. 5,344,793, discloses a method for forming within a microelectronics fabrication a cobalt silicide layer upon a crystalline silicon substrate at a temperature at or near room temperature. The method employs an argon ion sputtering of the crystalline silicon substrate to form a thin damaged region of the crystalline silicon substrate prior to depositing cobalt metal upon the thin damaged region of the crystalline silicon substrate to thus form by in-situ reaction at room temperature a cobalt silicide layer at the location of the thin damaged region of the crystalline silicon substrate.
Yet further, Roberts et al., in U.S. Pat. No. 4,470,189, discloses a method for forming a metal silicide polycide (metal silicidel/polysilicon stack) layer with improved linewidth control within a microelectronics fabrications. The method employs a photoresist lift-off stencil for forming a composite evaporated metal and silicon layer which is subsequently thermally annealed to form a metal silicide layer employed within the metal silicide polycide layer.
Still yet further, Wilber et al., in U.S. Statutory Invention Registration No. H 1543, discloses a microelectronics fabrication employing a cobalt silicide metal silicide layer or a nickel silicide metal silicide layer as an electrode substrate layer for a ferroelectric layer within the microelectronics fabrication. By employing the cobalt silicide metal silicide layer or the nickel silicide metal silicide layer as the electrode substrate layer, the ferroelectric layer may be formed epitaxially.
Still yet further, Hayashi et al., in U.S. Pat. No. 5,576,244, discloses a method for forming a metal silicide interconnect layer bridging from a silicon semiconductor substrate to a conductor layer formed over a dielectric isolation layer within a semiconductor integrated circuit microelectronics fabrication. Within the method there is employed a patterned silicon layer formed over portions of a metal silicide forming metal layer not in contact with the silicon semiconductor substrate to provide a silicon source layer when forming while employing a thermal annealing method the metal silicide interconnect layer by thermal annealing the patterned silicon layer and the metal silicide forming metal layer.
Finally, Wong et al., in U.S. Pat. No. 5,731,239, discloses a method for forming, with uniform and low contact resistance, a polycide gate electrode for use within a field effect transistor (FET) within a semiconductor integrated circuit microelectronics fabrication. The method employs an amorphizing ion implant into a polysilicon gate electrode prior to forming and thermally annealing upon the polysilicon gate electrode a metal silicide forming metal layer.
Desirable in the art of microelectronics fabrication are additional methods and materials which may be employed to form within microelectronics fabrications metal silicide layers. Particularly desirable in the art of microelectronics fabrication are additional methods and materials which may be employed within microelectronics fabrications to form metal silicide layers with uniformly low contact resistance and minimal process complexity.
It is towards the foregoing objects that the present invention is both generally and more specifically directed.